This invention relates to differential absolute delay equalization measuring circuits.
It is often necessary in circuits such as data switches to provide an analog signal which represents the system DADEing (Differential Absolute Delay Equalization). Once the DADEing has been determined, a correction can be made by inserting a delay into the leading data signal path to ensure that both data steams and both associated clocks are in phase. When the two signal paths have been properly DADEed, then switching between data sources can be accomplished without introducing data errors.
Heretofore, the DADEing was measured by a time measurement device such as an oscilloscope or elapse time clock. The time measurement device is triggered on by the leading edge of a pulse of the leading signal and turned off by the leading edge of a pulse of the following signal. Implementation of the Prior Art method required either manual intervention or complex timing and triggering circuits.
A circuit for measuring the Differential Absolute Delay Equalization between two data signals (each signal consisting of a data stream and its associated clock) is provided. The circuit generates an equalization error signal which is a composite of error signal and a pedestal voltage. The circuit also generates a replica of the pedestal voltage by taking the algebraic summation of the output of the comparison circuit and the complement of the output of the comparison circuit. The equalization error is the difference between the error signal and the replica pedestal voltage.
The invention provides for comparing two receive clock pulses (or data pulses) and generating an "OR" of the two receive clock pulses as well as the complementary form of the "OR" or "NOR" of the two circuitries in one embodiment. The replica pedestal voltage is generated in one of two ways, the preferred being by algebraically summing the "OR" and the "NOR" signals and using the resultant to subtract from the average of the "OR" of the two clock pulses to generate the differential absolute delay equalization error. The generating of the replica pedestal voltage from circuitry that is also used to provide the comparison output minimizes the effects of power supply fluctuations and temperature variations upon the circuitry because the voltage levels will track these fluctuations.
Many advantages of the present invention may be ascertained from a reading of the specification and the claims in conjunction with the drawings.